Fraunhofer Develops RISC-V Security Chip for Connected Devices

Fraunhofer IIS, AISEC, and EMFT are presenting a RISC-V secure element developed and manufactured in Germany. The OpenTitan-based chip combines open-source hardware with post-quantum cryptography and is designed to secure connected devices through a customizable hardware root of trust.

Hardware Security Anchor for Connected Devices

The RISC-V Secure Element is designed for industrial, infrastructure, and everyday devices. It can be used as a standalone chip or as a component in a system-on-chip.

As a hardware root of trust, it embeds security-critical functions directly into the silicon. For wireless IoT devices, this creates a foundation for trusted device identities, the protection of sensitive data, and cryptographic processes. At the same time, the development is intended to help ensure that requirements of the European Cyber Resilience Act are taken into account as early as the product design phase.

OpenTitan as a Transparent Hardware Foundation

The starting point is the open hardware design OpenTitan. The publicly accessible architecture can be independently verified, adapted, and further developed.

Building on this foundation, the three Fraunhofer Institutes developed a chip manufactured using GlobalFoundries’ 22-nanometer FDSOI technology in Dresden. Design and manufacturing in Germany ensure transparency throughout the value chain and guarantee access to the technology.

Customizable Variants Even in Smaller Quantities

In collaboration with GlobalFoundries, variants with additional interfaces, accelerators, or enhanced security features can be developed. Such customizations should also be possible in small and medium production runs.

This is relevant for specialized IoT applications where standard chips do not fully meet technical or regulatory requirements. In addition, the secure element can be integrated into larger SoC architectures as a customer-specific trust anchor.

Post-Quantum Cryptography for Long-Lived IoT Systems

Fraunhofer AISEC has implemented and accelerated post-quantum cryptography algorithms in hardware. Despite limited computing power, cryptographic operations are designed to remain within the millisecond range.

This is particularly relevant for long-lasting IoT devices in machines, buildings, vehicles, or critical infrastructure. Such systems must support security methods that remain viable over the long term.

“Cybersecurity cannot be added as an afterthought. It must be embedded in the silicon from the very beginning,” says Dr. Augusto Wankler Hoppe, technical project manager at Fraunhofer IIS.

Security Testing Down to the Chip Level

Fraunhofer AISEC examines the physical resilience of the secure element in its Common Criteria EAL7-certified hardware security laboratory using side-channel analyses, fault-based attacks, and optical methods.

Fraunhofer EMFT supplements these tests in a Common Criteria EAL6-certified laboratory with reverse engineering as well as light, infrared, and scanning electron microscopy. The certification levels apply to the testing laboratories, not to the secure element itself.

Relevance for Wireless IoT

For device manufacturers, system integrators, and solution providers, the RISC-V Secure Element offers a European hardware foundation for secure connected products. This approach is particularly relevant for industrial sensors, gateways, trackers, access systems, machine controls, and other long-lasting devices with wireless connectivity.

Further information can be found on the Fraunhofer IIS project page.